As is well known to those of skill in the art, integrated circuits, i.e., electronic components, are fabricated in an array on a wafer. The wafer is then cut, sometimes called diced, to singulate the integrated circuits from one another.
FIG. 1 is a cross-sectional view of a section of a wafer 10 being cut from a front-side surface 10F of wafer 10 in accordance with the prior art. Formed in wafer 10 were integrated circuits 12. Integrated circuits 12 were delineated by scribe lines 14, which included a first scribe line 14A and a second scribe line 14B, on front-side surface 10F of wafer 10. For example, scribe lines 14 were formed by selective etching of a silicon oxide layer 18 on front-side surface 10F.
To illustrate, first scribe line 14A delineated a first integrated circuit 12A from a second integrated circuit 12B. Each scribe line 14 had a width WF.
A back-side surface 10B of wafer 10 was attached to a tape 20. Wafer 10 was then sawed with a saw blade 22. Saw blade 22 was aligned with scribe lines 14 using an optical alignment system in a well-known manner. Saw blade 22 cut through wafer 10 along scribe lines 14. In this manner, integrated circuits 12 were singulated. Tape 20 supported wafer 10 during sawing and supported the singulated integrated circuits 12 after sawing was complete.
Generally, width WF of scribe lines 14 was sufficient to accommodate the width of the saw cut plus tolerance in the positioning of saw blade 22. Stated another way, width WF of scribe lines 14 was sufficiently large such that the saw cut made by saw blade 22 was always within a scribe line 14. For example, saw blade 22 is within scribe line 14B in FIG. 1.
Since the optical alignment system used scribe lines 14 directly to align saw blade 22, saw blade 22 was aligned to scribe lines 14 to within tight tolerance. Accordingly, scribe lines 14 were relatively narrow and, more particularly, were only slightly wider than saw blade 22. To illustrate, width WF was within the range of 0.002 inches (0.051 mm) to 0.008 inches (0.203 mm).
In certain instances, it was important to protect the front-side surface of the wafer during sawing, e.g., from shards and particulates generated during sawing. To protect the front-side surface, the wafer was sawed from the back-side surface of the wafer as discussed below in reference to FIG. 2.
FIG. 2 is a cross-sectional view of a section of a wafer 30 being cut from a back-side surface 30B of wafer 30 in accordance with the prior art. To protect a front-side surface 30F of wafer 30, front-side surface 30F was attached to a tape 32. Tape 32 supported wafer 30 during sawing.
Saw blade 22 was aligned with scribe lines 14-1 on front-side surface 30F of wafer 30 using a two-step process. First, tape 32 was aligned with scribe lines 14-1. Front-side surface 30F was attached to tape 32. Tape 32 had area greater than the area of front-side surface 30F such that tape 32 had an exposed region, which extended beyond wafer 30. Tape 32 had alignment marks in the exposed region of tape 32. As an example, see alignment holes 30a and 30b of Roberts, Jr. et al., U.S. Pat. No. 5,362,681, which is herein incorporated by reference in its entirety. In the above manner, scribe lines 14-1 were aligned with the alignment marks of tape 32.
Second, saw blade 22 was aligned with the alignment marks of tape 32. Wafer 30 was then sawed with saw blade 22 from back-side surface 30B. However, since saw blade 22 was aligned indirectly to scribe lines 14-1 using alignment marks of tape 32, a large tolerance was associated with the alignment of saw blade 22 to scribe lines 14-1.
To accommodate this large tolerance, each of scribe lines 14-1 had a relatively large width WB. More particularly, referring now to FIGS. 1 and 2 together, width WB of scribe lines 14-1 of wafer 30, which was designed to be cut from back-side surface 30B, was significantly larger than width WF of scribe lines 14 of wafer 10, which was designed to be cut from front-side surface 10F. To illustrate, width WB was approximately 0.012 inches (0.305 mm) or more.
Disadvantageously, forming scribe lines 14-1 with a relatively large width WB resulted in less integrated circuits 12 for any given size wafer 30 than the corresponding number of integrated circuits 12 formed in the same size wafer 10, i.e., there was a loss of yield of integrated circuits 12 from wafer 30. As a result, the cost of each integrated circuit 12 from wafer 30 was greater than the cost of each integrated circuit 12 from wafer 10. However, it is desirable to minimize the cost of each integrated circuit 12.